Semiconductor wafers are used in the production of semiconductor devices such as integrated circuit (IC) chips, silicon-on-insulator (SOI) wafers, and radio frequency-SOI (RF-SOI) wafers. Typically, the semiconductor wafers include a high resistivity substrate that can cause formation of a high conductivity inversion accumulation layer, which hinders the performance of the semiconductor devices.
In some processes, a layer, such as a polycrystalline silicon layer, is deposited onto a surface of the semiconductor wafer to provide a density charge trap and, thereby, inhibit the formation of the high conductivity inversion accumulation layer. For example, the layer can be deposited onto a surface that forms the interface between the high resistivity substrate and a buried oxide (BOX) to hinder the movement of charges across the interface. Once deposited, the layer tends to form a rough surface on the semiconductor wafer. Therefore, the rough surface of the semiconductor wafer needs to be further processed to have characteristics that meet the strict parameters for production of semiconductor devices, such as IC chips, SOI wafers, and RF-SOI wafers.
Typically, surfaces of semiconductor wafers are polished to improve surface characteristics including polycrystalline layer roughness and micro-defects. One way to polish a semiconductor wafer is referred to as chemical-mechanical polishing (CMP). CMP processes often use a circular polishing pad mounted on a turntable for driven rotation about a vertical axis and a mechanism for holding the wafer and forcing it to contact the polishing pad. The pad is rotated and the wafer is brought into contact with and forced against the pad by the polishing head. However, the polishing pad degrades over time and the polishing surface of the pad becomes uneven. Such pad wear impacts surface characteristics after polishing, which might cause the wafer to be unsatisfactory or require additional processing.
CMP processes may also significantly change the shape of the semiconductor wafer because portions of the semiconductor wafer are removed in unequal amounts and the thickness of the wafer then has variations. Accordingly, portions of the wafer may have areas of material that are thicker or thinner than necessary or optimal. These variations can cause waste and inefficiencies.
Accordingly, there is a need for a method to polish semiconductor wafers using improved pad wear processes and without substantially changing the shape of the semiconductor wafers. The methods should increase the quality of the wafer for use in high quality semiconductor devices such as IC chips, SOI wafers, and RF-SOI wafers.
This Background section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.